Virtualizing interrupt priority and delivery

ABSTRACT

Embodiments of processors, methods, and systems for virtualizing interrupt prioritization and delivery are disclosed. In one embodiment, a processor includes instruction hardware and execution hardware. The instruction hardware is to receive a plurality of instructions, including a first instruction to transfer the processor from a root mode to a non-root mode for executing guest software in a virtual machine, wherein the processor is to return to the root mode upon the detection of any of a plurality of virtual machine exit events. The execution hardware is to execute the first instruction, execution of the first instruction to include determining a first virtual processor-priority value and storing the first virtual processor-priority value in a virtual copy of a processor-priority field, where the virtual copy of the processor-priority field is a virtual resource corresponding to a physical resource associated with an interrupt controller.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application claims priority to U.S. patent application Ser.No. 13/325,714, filed Dec. 14, 2011.

BACKGROUND

1. Field

The present disclosure pertains to the field of information processing,and more particularly, to the field of virtualizing resources ininformation processing systems.

2. Description of Related Art

Generally, the concept of virtualization of resources in informationprocessing systems allows multiple instances of one or more operatingsystems (each, an “OS”) to run on a single information processingsystem, even though each OS is designed to have complete, direct controlover the system and its resources. Virtualization is typicallyimplemented by using software (e.g., a virtual machine monitor, or a“VMM”) to present to each OS a “virtual machine” (“VM”) having virtualresources, including one or more virtual processors, that the OS maycompletely and directly control, while the VMM maintains a systemenvironment for implementing virtualization policies such as sharingand/or allocating the physical resources among the VMs (the“virtualization environment”). Each OS, and any other software, thatruns on a VM is referred to as a “guest” or as “guest software,” while a“host” or “host software” is software, such as a VMM, that runs outsideof the virtualization environment.

A processor in an information processing system may supportvirtualization, for example, by operating in two modes—a “root” mode inwhich software runs directly on the hardware, outside of anyvirtualization environment, and a “non-root” mode in which software runsat its intended privilege level, but within a virtualization environmenthosted by a VMM running in root mode. In the virtualization environment,certain events, operations, and situations, such as external interruptsor attempts to access privileged registers or resources, may beintercepted, i.e., cause the processor to exit the virtualizationenvironment so that the VMM may operate, for example, to implementvirtualization policies (a “VM exit”). The processor may supportinstructions for establishing, entering, exiting, and maintaining avirtualization environment, and may include register bits or otherstructures that indicate or control virtualization capabilities of theprocessor.

BRIEF DESCRIPTION OF THE FIGURES

The present invention is illustrated by way of example and notlimitation in the accompanying figures.

FIG. 1 illustrates a virtualization architecture in which an embodimentof the present invention may provide for virtualizing interruptprioritization and delivery.

FIG. 2 illustrates a local APIC page in a processor in an embodiment ofthe present invention.

FIG. 3 illustrates a virtual machine control structure and a virtualAPIC page in an embodiment of the present invention.

FIGS. 4 to 9 illustrate method embodiments of the present invention.

DETAILED DESCRIPTION

Embodiments of processors, methods, and systems for virtualizinginterrupt prioritization and delivery are described below. In thisdescription, numerous specific details, such as component and systemconfigurations, may be set forth in order to provide a more thoroughunderstanding of the present invention. It will be appreciated, however,by one skilled in the art, that the invention may be practiced withoutsuch specific details. Additionally, some well known structures,circuits, and the like have not been shown in detail, to avoidunnecessarily obscuring the present invention.

The performance of a virtualization environment may be improved byreducing the frequency of VM exits. Embodiments of the invention may beused to reduce the frequency of VM exits associated with theprioritization and delivery of interrupts. An embodiment may be used tosupport the virtualization of a local Advanced Programmable InterruptController (“APIC”) in a processor in the Core® Processor Family fromIntel Corporation, and any other processor from any company, such as theAtom® Processor Family from Intel Corporation. In this embodiment,performance may be improved over a virtualization environment in whichguest accesses to the local APIC are intercepted by a VMM, byeliminating the need for a VM exit on some guest accesses to the localAPIC.

FIG. 1 illustrates virtualization architecture 100, in which anembodiment of the present invention may operate. In FIG. 1, bareplatform hardware 110 may be any data processing apparatus capable ofexecuting any OS, VMM, or other software. For example, bare platformhardware 110 may be that of a personal computer, mainframe computer,portable computer, handheld device, set-top box, server, or any othercomputing system. Bare platform hardware 110 includes processor 120 andmemory 130.

Processor 120 may be any type of processor, including a general purposemicroprocessor, such as a processor in the Core® Processor Family, theAtom® Processor Family, or other processor family from IntelCorporation, or another processor from another company, or a digitalsignal processor or microcontroller. Although FIG. 1 shows only one suchprocessor 120, bare platform hardware 110 may include any number ofprocessors, including any number of multicore processors, each with anynumber of execution cores and any number of multithreaded processors,each with any number of threads.

Memory 130 may be static or dynamic random access memory,semiconductor-based read only or flash memory, magnetic or optical diskmemory, any other type of medium readable by processor 120, or anycombination of such mediums. Processor 120, memory 130, and any othercomponents or devices of bare platform hardware 110 may be coupled to orcommunicate with each other according to any known approach, such asdirectly or indirectly through one or more buses, point-to-point, orother wired or wireless connections. Bare platform hardware 110 may alsoinclude any number of additional devices or connections.

Processor 120 may include interrupt controller 122 to receive, generate,prioritize, deliver, hold pending, or otherwise control or manageinterrupt requests. For example, interrupt controller 122 may be a localAPIC. Processor 120 may also include local APIC base address register orstorage location 123 to store a base address of a page or other rangesof addresses through which the registers or other control or statuslocations of an interrupt controller 122 may be accessed. In thisembodiment, local APIC base address register 123 is a 24-bit field of a64-bit register used to store the base address of 4-kilobyte local APICpage 200, as shown in FIG. 2. Local APIC page 200 includes task priorityregister (TPR) field 211 at offset 80h, processor priority register(PPR) field 212 at offset A0h, end-of-interrupt (EOI) register field 213at offset B0h, in-service register (ISR) field 214 at offset 100h,interrupt request register (IRR) field 215 at offset 200h, and interruptcommand register (ICR) field 216 at offset 300h.

Additionally, processor 120 includes instruction hardware 124 andexecution hardware 126. Instruction hardware 124 may include anycircuitry or other hardware, such as a decoder, to receive instructionsfor execution by processor 120. Execution hardware 126 may include anycircuitry or other hardware, such as an arithmetic logic unit, toexecute instructions for processor 120. Execution hardware may includeor be controlled by control logic 128. Control logic 128 may bemicrocode, programmable logic, hard-coded logic, or any other form ofcontrol logic within processor 120. In other embodiments, control logic128 may be implemented in any form of hardware, software, or firmware,such as a processor abstraction layer, within a processor or within anycomponent accessible or medium readable by a processor, such as memory130. Control logic 128 may cause execution logic 126 to execute methodembodiments of the present invention, such as the method embodimentsillustrated below in FIGS. 4 through 9, for example, by causingprocessor 120 to include the execution of one or more micro-operationsto support virtualization, in its response to virtualizationinstructions, other instructions from a host or guest, or eventsoccurring on bare platform hardware 110.

In addition to bare platform hardware 110, FIG. 1 illustrates VMM 140,VMs 150 and 160, and guest OSs and applications 152, 154, 156, 162, 164,and 166.

VMM 140 may be any software, firmware, or hardware host installed on oraccessible to bare platform hardware 110, to present VMs, i.e.,abstractions of bare platform hardware 110, to guests, or to otherwisecreate VMs, manage VMs, and implement virtualization policies. In otherembodiments, a host may be any VMM, hypervisor, OS, or other software,firmware, or hardware capable of controlling bare platform hardware 110.A guest may be any OS, any VMM, any hypervisor, or any application orother software.

Each guest expects to access physical resources, such as processor andplatform registers, memory, and input/output devices, of bare platformhardware 110, according to the architecture of the processor and theplatform presented in the VM. FIG. 1 shows two VMs, 150 and 160, withguest OS 152 and guest applications 154 and 156 installed on VM 150 andguest OS 162 and guest applications 164 and 166 installed on VM 160.Although FIG. 1 shows only two VMs and two applications per VM, anynumber of VMs may be created, and any number of applications may run oneach VM within the scope of the present invention.

A resource that can be accessed by a guest may either be classified as a“privileged” or a “non-privileged” resource. For a privileged resource,VMM 140 facilitates the functionality desired by the guest whileretaining ultimate control over the resource. Non-privileged resourcesdo not need to be controlled by VMM 140 and may be accessed directly bya guest.

Furthermore, each guest OS expects to handle various events such asexceptions (e.g., page faults, and general protection faults),interrupts (e.g., hardware interrupts and software interrupts), andplatform events (e.g., initialization and system management interrupts).These exceptions, interrupts, and platform events are referred tocollectively and individually as “events” herein. Some of these eventsare “privileged” because they must be handled by VMM 140 to ensureproper operation of VMs 150 and 160, protection of VMM 140 from guests,and protection of guests from each other.

At any given time, processor 120 may be executing instructions from VMM140 or any guest, thus VMM 140 or the guest may be running on, or incontrol of, processor 120. When a privileged event occurs or a guestattempts to access a privileged resource, a VM exit may occur,transferring control from the guest to VMM 140. After handling the eventor facilitating the access to the resource appropriately, VMM 140 mayreturn control to a guest. The transfer of control from VMM 140 to aguest (including an initial transfer to a newly created VM) is referredto as a “VM entry” herein.

In the embodiment of FIG. 1, processor 120 controls the operation of VMs150 and 160 according to data stored in virtual machine controlstructure (“VMCS”) 300, as shown in FIG. 3. VMCS 300 is a data structurethat may contain state of a guest or guests, state of VMM 140, executioncontrol information indicating how VMM 140 is to control operation of aguest or guests, information regarding VM exits and VM entries, anyother such information. Processor 120 reads information from VMCS 300 todetermine the execution environment of a VM and constrain its behavior.In this embodiment, VMCS 300 is stored in memory 130. In someembodiments, multiple VMCSs are used to support multiple VMs.

VMCS 300 may include fields, control bits, or other data structures tosupport the virtualization of an interrupt controller such as local APIC122. Execution hardware 126 and/or control logic 128 may refer to thesefields in VMCS 300 to determine how to manage a VM environment includingsupport for interrupt prioritization and delivery. For example, virtualinterrupt delivery control indicator 310 may be set to enable thevirtualization of interrupt prioritization and delivery in non-rootmode, as described below. In the description of this embodiment, anindicator such as virtual interrupt delivery control 310 may be a bitthat is set to a high or logical ‘1’ value to enable or cause a desiredeffect (or cleared to a low or logical ‘0’ value to cause the opposite),but any logic convention or nomenclature may be used within the scope ofthe present invention.

Also in VMCS 300, virtual APIC base address field 320 may be used tostore a base address of a page or other region of memory 130 at whichvirtual copies of one or more of the register or other control or statuslocations of an interrupt controller may be stored. In this embodiment,virtual APIC base address field 320 is used to store the base address ofvirtual APIC page 330. Virtual APIC page 330 includes virtual TPR field331, virtual PPR field 332, virtual EOI field 333, virtual ISR field334, virtual IRR field 335, and virtual ICR field 336. For example,virtual APIC base address field 320 may be a 24-bit field specifying thelocation in memory of 4-kilobyte virtual APIC page 330, such that avirtual copy of a task priority class may be stored in bits 7:4 ofvirtual TPR field 331 and a virtual copy of a task priority subclass maybe stored in bits 3:0 of virtual TPR field 331, at offset 80h of virtualAPIC page 330, and a virtual copy of a processor priority class may beread from bits 7:4 of virtual PPR field 332 and a virtual copy of aprocessor priority subclass may be read from bits 3:0 of virtual PPRfield 332, at offset A0h of virtual APIC page 330. Also, a virtual EOIregister may be provided using virtual EOI field 333 at offset B0h ofvirtual APIC page 330, a virtual ISR may be provided using virtual ISRfield 334 at offset 100h of virtual APIC page 330, and a virtual IRR maybe provided using virtual IRR field 335 at offset 200h of virtual APICpage 330.

VMCS 300 may also include RVI field 340 for the highest priority virtualinterrupt requesting service, SVI field 350 for the highest priorityvirtual interrupt in service, and EOI bitmap field 360 for a 256-entryEOI bitmap. The use of these three fields is explained below.

FIGS. 4 through 9 illustrate embodiments of the present invention inmethods for virtualizing interrupt prioritization and delivery. Althoughmethod embodiments are not limited in this respect, reference is made tovirtualization architecture 100 of FIG. 1, local APIC page 200 of FIG.2, and VMCS 300 of FIG. 3 to describe the method embodiments of FIGS. 4through 9. Each Figure may include some actions performed by software(e.g., a VMM) and other actions performed by hardware. However, softwareand/or hardware may perform additional actions (not shown) in connectionwith the actions shown.

FIG. 4 illustrates method 400, a method embodiment of the presentinvention that may be performed in connection with other methodembodiments of the present invention, such as methods 500, 600, 700,800, and 900. Method 400 may be performed as part of the initializationof embodiments of the invention on a particular virtual processor.

In box 410 of FIG. 4, a VMM (e.g., VMM 140) creates a VMCS (e.g., VMCS300) for a VM (e.g., VM 150). In boxes 420 through 430, VMM 140configures VMCS 300 to implement virtualization of interruptprioritization and delivery. In box 420, memory (e.g., a page in memory130) is allocated for a virtual APIC page (e.g., virtual APIC page 330).In box 422, a base address for virtual APIC page 330 is stored invirtual APIC base address field 320. In box 424, virtual interruptdelivery control indicator 310 is set to enable the virtualization ofinterrupt prioritization and delivery in non-root mode. In box 426, VMM140 may store initialization data (e.g., all zeroes) in RVI field 340.In box 428, VMM 140 may store initialization data (e.g., all zeroes) inSVI field 350. In box 430, VMM 140 may store initialization data invirtual APIC page 330.

FIG. 5 illustrates method 500, a method embodiment of the presentinvention that may be performed in connection with other methodembodiments of the present invention, such as methods 400, 600, 700,800, and 900. Method 500 may be performed in connection with a VM entry,when virtualization of interrupt prioritization and delivery in non-rootmode is enabled, for example, by the setting of virtual interruptdelivery control indicator 210.

In box 502, VMM 140 may set the bit in virtual IRR 335 corresponding tothe interrupt vector of the interrupt requesting service. Note that box502 may be repeated for any other interrupts requesting service. In box504, VMM 140 may store an interrupt vector of an interrupt requestingservice in RVI field 340; for example, RVI field 340 may be set (or maybe left as is) with the maximum of the old RVI value and the highestinterrupt vector from any repetition of box 502. In box 506, aninstruction to transfer control to VM 150 (a “VM enter” instruction) isissued by VMM 140.

In box 510 of method 500, instruction hardware 124 of processor 120receives a VM enter instruction. In boxes 512 to 516, execution hardware126 of processor 120 executes portions of the VM enter instructionrelating to embodiments of the present invention. Execution of the VMinstruction may include saving of host state, loading of guest state,and any other operations known in the art, in addition to those shownhere. In box 512, execution hardware 126 determines a new virtualprocessor priority value by computing the maximum of the value in SVIfield 350 and the value in virtual TPR field 331. In box 514, executionhardware 126 stores the new virtual processor priority value in virtualPPR field 332. In box 516, execution hardware 126 compares the value inRVI field 340 to the value in virtual PPR field 332, and if the RVIfield 340 value is greater than the virtual PPR field 332 value, method500 continues in box 520, but if not, method 500 continues in box 522.In box 520, a VM entry occurs and the pending virtual interruptcorresponding to the RVI field 340 value is recognized. In box 522, a VMentry completes but any virtual interrupt corresponding to the RVI field340 value is held pending.

FIG. 6 illustrates method 600, a method embodiment of the presentinvention that may be performed in connection with other methodembodiments of the present invention, such as methods 400, 500, 700,800, and 900. Method 600 may be performed when virtualization ofinterrupt prioritization and delivery in non-root mode is enabled, forexample, by the setting of virtual interrupt delivery control indicator210. Method 600 may be performed entirely in non-root mode without a VMexit, in connection with a write by guest software to an APIC register(e.g., TPR).

In box 610 of method 600, guest software attempts to write a new taskpriority value to TPR field 211 of local APIC page 200. In response toguest software attempting to write to TPR field 211, execution hardware126 performs boxes 612 to 622 instead of a write to TPR field 211 or aVM exit occurring. In box 612, execution hardware 126 passes the writeto virtual TPR field 331 on virtual APIC page 330. In box 614, executionhardware 126 determines a new virtual processor priority value bycomputing the maximum of the virtual task priority value from virtualTPR field 331 and the value in SVI field 350. In box 616, executionhardware 126 stores the new virtual processor priority value in virtualPPR field 332. In box 618, execution hardware 126 compares the value inRVI field 340 to the virtual PPR field 332 value, and if the RVI field340 value is greater than the virtual PPR field 332, method 600continues in box 620, but if not, method 600 continues in box 622. Inbox 620, execution hardware 126 recognizes the pending virtual interruptcorresponding to the RVI field 340 value. In box 622, execution hardware126 holds pending any virtual interrupt corresponding to the RVI field340 value.

FIG. 7 illustrates method 700, a method embodiment of the presentinvention that may be performed in connection with other methodembodiments of the present invention, such as methods 400, 500, 600,800, and 900. Method 700 may be performed when virtualization ofinterrupt prioritization and delivery in non-root mode is enabled, forexample, by the setting of virtual interrupt delivery control indicator210. Method 700 may be performed entirely in non-root mode without a VMexit, in connection with an attempt by guest software to send aself-IPI, for example, by writing to an APIC register (e.g., ICR 216 ora special self-IPI register).

In box 710 of method 700, guest software running on processor 120attempts to direct processor 120 to send an inter-processor-interrupt toitself (i.e., send a “self-IPI”); for example, by writing to ICR 216 oflocal APIC page 200. In response to guest software attempting to send aself-IPI, execution hardware 126 performs boxes 712 to 726 instead of awrite to ICR 216 or a VM exit occurring. In box 712, execution hardware126 passes the write to virtual ICR 336 on virtual APIC page 330. In box714, execution hardware 126 determines the vector of the interrupt to besent, e.g., by reading the vector field of virtual ICR 336. In box 716,execution hardware 126 sets the bit corresponding to that vector invirtual IRR field 335, to indicate an interrupt corresponding to thatvector is pending. In box 718, execution hardware 126 determines a newRVI value by computing the maximum of this vector and the value in RVIfield 340. In box 720, execution hardware 126 stores the new RVI valuein RVI field 340. In box 722, execution hardware 126 compares the newRVI value to the value in virtual PPR field 332, and if the new RVIvalue is greater than the virtual PPR field 332 value, method 700continues in box 724, but if not, method 700 continues in box 726. Inbox 724, execution hardware 126 recognizes the pending virtual interruptcorresponding to the new RVI value. In box 726, execution hardware 126holds pending any virtual interrupt corresponding to the new RVI value.

FIG. 8 illustrates method 800, a method embodiment of the presentinvention that may be performed in connection with other methodembodiments of the present invention, such as methods 400, 500, 600,700, and 900. Method 800 may be performed when virtualization ofinterrupt prioritization and delivery in non-root mode is enabled, forexample, by the setting of virtual interrupt delivery control indicator210. Method 800 may be performed in connection with an attempt by guestsoftware to write to EOI register field 213 of local APIC page 200.

In box 810 of method 800, guest software running on processor 120attempts to write to EOI register field 213 of local APIC page 200. Inresponse to guest software attempting to write to EOI register field213, execution hardware 126 performs boxes 812 to 822 instead of an EOIwrite to EOI register field 213 occurring. In box 812, executionhardware 126 passes the write to virtual EOI register field 333 onvirtual APIC page 330. In box 814, execution hardware 126 clears the bitcorresponding to the current SVI 350 field value in virtual ISR field334. In box 816, execution hardware 126 stores, in SVI field 350, theindex of the highest priority bit still set in virtual ISR field 334 (orzero if no bit is set). In box 818, execution hardware 126 determines anew processor priority value by computing the maximum of the new SVIvalue and the virtual TPR field 331 value. In box 820, executionhardware 126 stores the new processor priority value in virtual PPRfield 332. In box 822, execution hardware 126 determines whether the bitin EOI bitmap field 360 corresponding to the old SVI value is set, and,if so, method 800 continues in box 830, but if not, method 800 continuesin box 824. In box 830, a VM exit occurs. In box 824, execution hardware126 compares the value in RVI field 340 to the value in virtual PPRfield 332, and if the RVI field 340 value is greater than the virtualPPR field 332 value, method 800 continues in box 826, but if not, method800 continues in box 828. In box 826, execution hardware 126 recognizesthe pending virtual interrupt corresponding to the RVI field 340 value.In box 828, execution hardware 126 holds pending any virtual interruptcorresponding to the RVI field 340 value.

FIG. 9 illustrates method 900, a method embodiment of the presentinvention that may be performed in connection with other methodembodiments of the present invention, such as methods 400, 500, 600,700, and 800. Method 900 may be performed when virtualization ofinterrupt prioritization and delivery in non-root mode is enabled, forexample, by the setting of virtual interrupt delivery control indicator210. Method 900 may be performed entirely in non-root mode without a VMexit, in connection with the delivery of a virtual interrupt.

In box 902 of method 900, an instruction boundary is reached, forexample during the execution of guest software on a virtual machine. Inbox 904, execution hardware 126 determines whether a virtual interrupthas been recognized, for example from box 520, 620, 724, or 826 ofmethods 500, 600, 700, or 800, respectively. If a virtual interrupt hasnot been recognized, then method 900 continues to box 930; if not,method 900 continues to box 910.

In box 910, execution hardware 126 determines whether delivery ofvirtual interrupts is masked at the instruction boundary (for example,because the interrupt flag in the EFLAGS register of processor 120 iscleared). If delivery of virtual interrupts is masked, then method 900continues to box 930; if not, method 900 continues in box 912. In box912, execution hardware 126 clears the bit corresponding to the RVIfield 340 value in virtual IRR field 335. In box 914, execution hardware126 sets the bit corresponding to the RVI field 340 value in virtual ISRfield 334. In box 916, execution hardware 126 stores the RVI field 340value in SVI field 350. In box 918, execution hardware 126 stores theRVI field 340 value in virtual PPR field 332. In box 920, executionhardware 126 stores, in RVI field 340, the index of the highest prioritybit still set in virtual IRR field 335 (or zero if no bit is set). Inbox 922, execution hardware 126 holds pending any interruptcorresponding to the new RVI value. In box 924, execution hardware 132delivers, to the guest software running on processor 120, the interruptwith the vector corresponding to the old RVI value (for example, byusing it to select a gate in the interrupt descriptor table).

In box 930, the next instruction is executed.

Within the scope of the present invention, the methods illustrated inFIGS. 4 through 9 may be performed in a different order, withillustrated boxes omitted, with additional boxes added, or with acombination of reordered, omitted, or additional boxes.

Thus, processors, methods, and systems for virtualizing interruptprioritization and delivery have been disclosed. While certainembodiments have been described, and shown in the accompanying drawings,it is to be understood that such embodiments are merely illustrative andnot restrictive of the broad invention, and that this invention not belimited to the specific constructions and arrangements shown anddescribed, since various other modifications may occur to thoseordinarily skilled in the art upon studying this disclosure. In an areaof technology such as this, where growth is fast and furtheradvancements are not easily foreseen, the disclosed embodiments may bereadily modifiable in arrangement and detail as facilitated by enablingtechnological advancements without departing from the principles of thepresent disclosure or the scope of the accompanying claims.

What is claimed is:
 1. A processor comprising: instruction hardware toreceive a plurality of instructions, including a first instruction totransfer the processor from a root mode to a non-root mode for executingguest software in a virtual machine, wherein the processor is to returnto the root mode upon the detection of any of a plurality of virtualmachine exit events; and execution hardware to execute the firstinstruction, execution of the first instruction to include determining afirst virtual processor-priority value and storing the first virtualprocessor-priority value in a virtual copy of a processor-priorityfield, where the virtual copy of the processor-priority field is avirtual resource corresponding to a physical resource associated with aninterrupt controller.
 2. The processor of claim 1, wherein the executionhardware is to determine the processor-priority value by computing themaximum of a highest priority virtual interrupt in-service field of avirtual machine control structure and a virtual task-priority registervalue.
 3. The processor of claim 1, wherein the execution hardware isalso to determine whether a virtual interrupt is to be recognized bycomparing a highest priority virtual interrupt-requested field of avirtual machine control structure and the first virtualprocessor-priority value.
 4. The processor of claim 1, wherein theexecution hardware is also to respond, within the non-root mode, to anattempt by the guest software to write a task-priority value to atask-priority register by computing the maximum of the task-priorityvalue and a highest priority virtual interrupt in-service field of avirtual machine control structure to determine a second virtualprocessor-priority value.
 5. The processor of claim 4, wherein theexecution hardware is also to determine whether a virtual interrupt isto be recognized by comparing a highest priority virtualinterrupt-requested field of a virtual machine control structure and thesecond virtual processor-priority value.
 6. The processor of claim 1,wherein the execution hardware is also to respond, within the non-rootmode, to an attempt by the guest software to send a self-interprocessorinterrupt by computing the maximum of a self-interprocessor interruptvector and a highest priority virtual interrupt-requested field of avirtual machine control structure to determine a new highest priorityvirtual interrupt-requested value.
 7. The processor of claim 6, whereinthe execution hardware is also to determine whether a virtual interruptis to be recognized by comparing the new highest priority virtualinterrupt-requested value and the first virtual processor-priorityvalue.
 8. The processor of claim 1, wherein the execution hardware isalso to respond, within the non-root mode, to an attempt by the guestsoftware to write to an end-of-interrupt register by clearing a bit in avirtual copy of an in-service register, the bit corresponding to ahighest priority virtual interrupt in-service field in a virtual machinestructure.
 9. The processor of claim 3, wherein the execution hardwareis also to determine whether delivery of virtual interrupts is masked atan instruction boundary and deliver the virtual interrupt if delivery isunmasked.
 10. A method comprising: receiving, by a processor, aninstruction to transfer the processor from a root mode to a non-rootmode for executing guest software in a virtual machine, wherein theprocessor is to return to the root mode upon the detection of any of aplurality of virtual machine exit events; executing, by the processor,the instruction, where execution includes determining a first virtualprocessor-priority value and storing the first virtualprocessor-priority value in a virtual copy of a processor-priorityfield, where the virtual copy of the processor-priority field is avirtual resource corresponding to a physical resource associated with aninterrupt controller.
 11. The method of claim 10, wherein determiningthe processor-priority value includes computing the maximum of a highestpriority virtual interrupt in-service field of a virtual machine controlstructure and a virtual task-priority register value.
 12. The method ofclaim 10, further comprising determining whether a virtual interrupt isto be recognized by comparing a highest priority virtualinterrupt-requested field of a virtual machine control structure and thefirst virtual processor-priority value.
 13. The method of claim 10,further comprising responding, within the non-root mode, to an attemptby the guest software to write a task priority value to a task-priorityregister by computing the maximum of the task-priority value and ahighest priority virtual interrupt in-service field of a virtual machinecontrol structure to determine a second virtual processor-priorityvalue.
 14. The method of claim 13, further comprising determiningwhether a virtual interrupt is to be recognized by comparing a highestpriority virtual interrupt-requested field of a virtual machine controlstructure and the second virtual processor-priority value.
 15. Themethod of claim 10, further comprising responding, within the non-rootmode, to an attempt by the guest software to send a self-interprocessorinterrupt by computing the maximum of a self-interprocessor interruptvector and a highest priority virtual interrupt-requested field of avirtual machine control structure to determine a new highest priorityvirtual interrupt-requested value.
 16. The method of claim 15, furthercomprising determining whether a virtual interrupt is to be recognizedby comparing the new highest priority virtual interrupt-requested valueand the first virtual processor-priority value.
 17. The method of claim10, further comprising responding, within a non-root mode, to an attemptby the guest software to write to an end-of-interrupt register byclearing a bit in a virtual copy of an in-service register, the bitcorresponding to a highest priority virtual interrupt in-service fieldin a virtual machine structure.
 18. The method of claim 17, furthercomprising determining whether delivery of virtual interrupts is maskedat an instruction boundary and delivering the virtual interrupt ifdelivery is unmasked.
 19. A system comprising: a memory; and a processorincluding instruction hardware to receive a plurality of instructions,including a first instruction to transfer the processor from a root modeto a non-root mode for executing guest software in a virtual machine,wherein the processor is to return to the root mode upon the detectionof any of a plurality of virtual machine exit events; and executionhardware to execute the first instruction, execution of the firstinstruction to include determining a virtual processor-priority valueand storing the first virtual processor-priority value in the memory ina virtual copy of a processor-priority field, where the virtual copy ofthe processor-priority field is a virtual resource corresponding to aphysical resource associated with an interrupt controller.
 20. Thesystem of claim 19, wherein the execution hardware is also to determinewhether a virtual interrupt is to be recognized by comparing a highestpriority virtual interrupt-requested field in a virtual machine controlstructure in the memory and the virtual processor-priority value.